1. Repositório PUCRS

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Resultados 1-10 de 21 (Tiempo de búsqueda: 0.002 Segundos).
Impacto del ítem:
Fecha de PublicaciónTítuloAutor(s)
2012A Generic FPGA Emulation FrameworkFernando Gehm Moraes; Matheus Moreira; Carlo Lucas; Dairan Correa; Douglas Cardoso; Maurício Magnaguagno; Guilherme Castilhos; Ney Laert Vilar Calazans
2012HardNoC: A Platform to Validate Networks on Chip through FPGA PrototypingGuilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Rafael Soares
2012Power Consumption Reduction in MPSoCs through DFSThiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2011A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCsThiago Raupp da Rosa; Guilherme Montez Guindani; Douglas Maciel Cardoso; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2011Adapting a C-Element Design Flow for Low PowerMatheus Moreira; Bruno Oliveira; Julian Pontes; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2021A differential IR-UWB transmitter using PAM modulation with adaptive PSDMOREIRA, LUIZ CARLOS; VICTOR, MARCUS HENRIQUE; SAOTOME, OSAMU; HECK, GUILHERME; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2011CAFES: A framework for intrachip application modeling and communication architecture designCésar Augusto Missio Marcon; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Fernando Gehm Moraes; Altamiro Amadeu Susin; Edson I. Moreno
2005Design and Prototyping of an SDH-E1 Mapper Soft-coreCésar Augusto Missio Marcon; José Santanna Palma; Ney Laert Vilar Calazans; Fernando Gehm Moraes

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