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Issue Date	Title	Author(s)
2016	Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications	Felipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho; Sergio Bampi; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Matheus Trevisan Moreira
2017	A Comparison of Asynchronous QDI Templates Using Static Logic	Ricardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015	A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework	Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015	Blade - A Timing Violation Resilient Asynchronous Template	Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2017	Sleep Convention Logic Isochronic Fork: an Analysis	Ricardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2016	Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications	Ramy Nagy Tadros; Weizhe Hua; Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015	A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies	Ajay Singhvi; Matheus Trevisan Moreira; Ramy Nagy Tadros; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015	Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits	Guilherme Heck; Leandro Sehnem Heck; Ajay Singhvi; Matheus Trevisan Moreira; Ney Laert Vilar Calazans; Peter Anthony Beerel
2017	Hardening C-elements Against Metastability	Leandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2016	ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous Design	Carlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans