Repositório PUCRS: Búsqueda

Búsqueda

Resultados 1-9 de 9 (Tiempo de búsqueda: 0.001 Segundos).

Anterior
1
Siguiente

Impacto del ítem:

Fecha de Publicación	Título	Autor(s)
2014	A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design	Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
2014	Quasi-Delay-Insensitive Return-to-One Design	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014	Automated Synthesis of Cell Libraries for Asynchronous Circuits	Matheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans
2014	Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis	Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
2014	Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2014	A Design Flow for Physical Synthesis of Digital Cells with ASTRAN	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2014	Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?	Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins; André Inácio Reis; Renato Perez Ribas; Ney Laert Vilar Calazans
2014	Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?	Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014	A monitored NoC with runtime path adaptation	Edson I. Moreno; Thais Christina Webber Dos Santos; César Augusto Missio Marcon; Fernando Gehm Moraes; Ney Laert Vilar Calazans