Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/13960
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dc.contributor.authorMatheus Trevisan Moreira-
dc.contributor.authorNey Laert Vilar Calazans-
dc.date.accessioned2019-02-12T12:04:15Z-
dc.date.available2019-02-12T12:04:15Z-
dc.date.issued2014-
dc.identifier.urihttp://hdl.handle.net/10923/13960-
dc.language.isoen-
dc.relation.ispartofProceedings of the DATE 2014 PhD Forum, 2014, Alemanha.-
dc.rightsopenAccess-
dc.subjectAsynchronous Circuits-
dc.subjectQDI-
dc.subjectReturn-to-one-
dc.titleQuasi-Delay-Insensitive Return-to-One Design-
dc.typeconferenceObject-
dc.date.updated2019-02-12T12:04:14Z-
Appears in Collections:Apresentação em Evento

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