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Resultados 1-10 de 47 (Tiempo de búsqueda: 0.001 Segundos).
Impacto del ítem:
Fecha de PublicaciónTítuloAutor(s)
2012A Generic FPGA Emulation FrameworkFernando Gehm Moraes; Matheus Moreira; Carlo Lucas; Dairan Correa; Douglas Cardoso; Maurício Magnaguagno; Guilherme Castilhos; Ney Laert Vilar Calazans
2012HardNoC: A Platform to Validate Networks on Chip through FPGA PrototypingGuilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Rafael Soares
2012Power Consumption Reduction in MPSoCs through DFSThiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2011A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCsThiago Raupp da Rosa; Guilherme Montez Guindani; Douglas Maciel Cardoso; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2011Adapting a C-Element Design Flow for Low PowerMatheus Moreira; Bruno Oliveira; Julian Pontes; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2016Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling ApplicationsFelipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho; Sergio Bampi; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Matheus Trevisan Moreira
2017A Comparison of Asynchronous QDI Templates Using Static LogicRicardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017Go Functional Model for a RISC-V Asynchronous Organization - ARVMarcos Luiggi Lemos Sartori; Ney Laert Vilar Calazans
2015A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA FrameworkMatheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans