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Fecha de Publicación	Título	Autor(s)
2014	A Design Flow for Physical Synthesis of Digital Cells with ASTRAN	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2013	Parity Check for m-of-n Delay Insensitive Codes	Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014	Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?	Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins; André Inácio Reis; Renato Perez Ribas; Ney Laert Vilar Calazans
2013	LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans; Luciano Copello Ost
2012	Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects	PONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2013	H2A: A Hardened Asynchronous Network on Chip	Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014	Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?	Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2012	An accurate Single Event Effect digital design flow for reliable system level design	PONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2013	NCL+: Return-to-One Null Convention Logic	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2013	Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow	Matheus Trevisan Moreira; Ney Laert Vilar Calazans