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Issue Date	Title	Author(s)
2012	A Generic FPGA Emulation Framework	Fernando Gehm Moraes; Matheus Moreira; Carlo Lucas; Dairan Correa; Douglas Cardoso; Maurício Magnaguagno; Guilherme Castilhos; Ney Laert Vilar Calazans
2012	HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping	Guilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Rafael Soares
2012	Power Consumption Reduction in MPSoCs through DFS	Thiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2012	Impact of C-Elements in Asynchronous Circuits	Matheus Moreira; Bruno Oliveira; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2011	A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCs	Thiago Raupp da Rosa; Guilherme Montez Guindani; Douglas Maciel Cardoso; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2011	Adapting a C-Element Design Flow for Low Power	Matheus Moreira; Bruno Oliveira; Julian Pontes; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2016	Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications	Felipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho; Sergio Bampi; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Matheus Trevisan Moreira
2017	A Comparison of Asynchronous QDI Templates Using Static Logic	Ricardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017	Go Functional Model for a RISC-V Asynchronous Organization - ARV	Marcos Luiggi Lemos Sartori; Ney Laert Vilar Calazans
2015	A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework	Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans