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Data de publicação	Título	Autor(es)
2012	A Generic FPGA Emulation Framework	Fernando Gehm Moraes; Matheus Moreira; Carlo Lucas; Dairan Correa; Douglas Cardoso; Maurício Magnaguagno; Guilherme Castilhos; Ney Laert Vilar Calazans
2012	HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping	Guilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Rafael Soares
2012	Power Consumption Reduction in MPSoCs through DFS	Thiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2012	Impact of C-Elements in Asynchronous Circuits	Matheus Moreira; Bruno Oliveira; Fernando Gehm Moraes; Ney Laert Vilar Calazans
2012	Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects	PONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2012	An accurate Single Event Effect digital design flow for reliable system level design	PONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2012	Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes	MOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
2012	A spectrum of MPSoC models for design space exploration and its use	PETRY, CARLOS A.; WACHTER, EDUARDO W.; DE CASTILHOS, GUILHERME M.; MORAES, FERNANDO G.; Ney Laert Vilar Calazans
2012	Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits	MOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
2012	Electrical characterization of a C-Element with LiChEn	MOREIRA, MATHEUS T.; Ney Laert Vilar Calazans