1. Repositório PUCRS

Browsing by Author Ney Laert Vilar Calazans

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Issue DateTitleAuthor(s)
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes, et al
2013Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancyYan Ghidini de Souza; Matheus Moreira; Lucas Brahm, et al
2020Leveraging QDI Robustness to Simplify the Design of IoT CircuitsSARTORI, MARCOS L. L.; WUERDIG, RODRIGO N.; MOREIRA, MATHEUS T., et al
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2005Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy EstimationPALMA, JOSE CARLOS S.; César Augusto Missio Marcon; Fernando Gehm Moraes, et al
2002Modelagem e Descrição de Sistemas Computacionais - Um Estudo de Caso de Comparação das Linguagens VHDL e SDLCésar Augusto Missio Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes, et al
2002Modeling of Embedded Digital Systems from SDL Language: a Case StudyCésar Augusto Missio Marcon; Fabiano Passuelo Hessel; Alexandre Amory, et al
2005Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCsCésar Augusto Missio Marcon; José Santanna Palma; Ney Laert Vilar Calazans, et al
2005Models for Embedded Application Mapping onto NoCs: Timing AnalysisCésar Augusto Missio Marcon; KREUTZ, M.; Altamiro Amadeu Susin, et al
2014MoNoC: A monitored network on chip with path adaptation mechanismMORENO, EDSON; Thais Christina Webber Dos Santos; César Augusto Missio Marcon, et al
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Parity Check for m-of-n Delay Insensitive CodesJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2012Power Consumption Reduction in MPSoCs through DFSThiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans, et al
2002Prototyping of embedded digital systems from SDL language: a case studyCésar Augusto Missio Marcon; Fabiano Passuelo Hessel; Alexandre Amory, et al
2019Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA ToolsMarcos Luiggi Lemos Sartori; Rodrigo Nogueira Wuerdig; Matheus Trevisan Moreira, et al
2021Quasi Delay Insensitive FIFOs: Design Choices Exploration and ComparisonRODOLFO, TACIANO A.; SARTORI, MARCOS L. L.; MOREIRA, MATHEUS T., et al
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2002Requirements, primitives and models for systems specificationCésar Augusto Missio Marcon; Ney Laert Vilar Calazans; MORAES, F.G.
2012Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuitsMOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
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