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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/13389
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dc.contributor.authorBORTOLON, FELIPE T.-
dc.contributor.authorFernando Gehm Moraes-
dc.contributor.authorMOREIRA, MATHEUS T.-
dc.contributor.authorBAMPI, SERGIO-
dc.date.accessioned2018-12-10T12:46:30Z-
dc.date.available2018-12-10T12:46:30Z-
dc.date.issued2017-
dc.identifier.isbn9781450351065-
dc.identifier.urihttp://hdl.handle.net/10923/13389-
dc.language.isoen-
dc.relation.ispartofProceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17, 2017, Estados Unidos.-
dc.rightsopenAccess-
dc.subjectStatic Noise Margin-
dc.subjectSubthreshold-
dc.titleEstimation methods for static noise margins in CMOS subthreshold logic circuits-
dc.typeconferenceObject-
dc.date.updated2018-12-10T12:46:29Z-
dc.identifier.doiDOI:10.1145/3109984.3109998-
Appears in Collections:Apresentação em Evento

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