1. Repositório PUCRS

Visualizando por Autor Matheus Trevisan Moreira

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Fecha de PublicaciónTítuloAutor(s)
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, etc.
2019Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA ToolsMarcos Luiggi Lemos Sartori; Rodrigo Nogueira Wuerdig; Matheus Trevisan Moreira, etc.
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira, etc.
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans, etc.
2014Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins, etc.
2017Sleep Convention Logic Isochronic Fork: an AnalysisRicardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira, etc.
2015TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and OptimizationMatheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel, etc.
2018Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient TemplateKUENTZER, FELIPE A.; JURACY, LEONARDO; Matheus Trevisan Moreira, etc.
2015Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous DesignMatheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2013Voltage Scaling on C-Elements: A Speed, Power and Energy Efficiency AnalysisMatheus Trevisan Moreira; Ney Laert Vilar Calazans
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