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Browsing by Author Matheus Trevisan Moreira

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Issue Date	Title	Author(s)
2015	Performance Optimization and Analysis of Blade Designs Under Delay Variability	Dylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2019	Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools	Marcos Luiggi Lemos Sartori; Rodrigo Nogueira Wuerdig; Matheus Trevisan Moreira, et al
2014	Quasi-Delay-Insensitive Return-to-One Design	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014	Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?	Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira, et al
2015	SDDS-NCL Design: Analysis of Supply Voltage Scaling	Ricardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans, et al
2014	Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?	Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins, et al
2017	Sleep Convention Logic Isochronic Fork: an Analysis	Ricardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira, et al
2015	TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization	Matheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel, et al
2018	Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template	KUENTZER, FELIPE A.; JURACY, LEONARDO; Matheus Trevisan Moreira, et al
2015	Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous Design	Matheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2013	Voltage Scaling on C-Elements: A Speed, Power and Energy Efficiency Analysis	Matheus Trevisan Moreira; Ney Laert Vilar Calazans

Showing rec. 21 to 31 of 31 ◄ previous