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Fecha de Publicación	Título	Autor(s)
2013	Design of NCL Gates with the ASCEnD Flow	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2014	Quasi-Delay-Insensitive Return-to-One Design	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015	Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous Design	Matheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2014	Automated Synthesis of Cell Libraries for Asynchronous Circuits	Matheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans
2015	SDDS-NCL Design: Analysis of Supply Voltage Scaling	Ricardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2014	Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis	Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
2015	TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization	Matheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel; Ney Laert Vilar Calazans
2013	A Flexible Soft IP Core for Standard Implementations of Elliptic Curve Cryptography in Hardware	Bruno Fin Ferreira; Ney Laert Vilar Calazans
2014	Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2013	ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans