1. Repositório PUCRS

Percorrendo por Assunto Asynchronous Circuits

Ir para: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
ou digite as primeiras letras:  
Mostrando regs. 9 a 27 de 27   ◄ anterior   
Data de publicaçãoTítuloAutor(es)
2013ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous DesignMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2019Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT VariationsWUERDIG, RODRIGO N.; SARTORI, MARCOS L. L.; Ney Laert Vilar Calazans
2019Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT VariationsWUERDIG, RODRIGO N.; SARTORI, MARCOS L. L.; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr., et al
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang, et al
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2021Quasi Delay Insensitive FIFOs: Design Choices Exploration and ComparisonRODOLFO, TACIANO A.; SARTORI, MARCOS L. L.; MOREIRA, MATHEUS T., et al
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2012Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codesMOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
2021Robust and Energy-Efficient Hardware: The Case for Asynchronous DesignNey Laert Vilar Calazans; Taciano Ares Rodolfo; Marcos Luiggi Lemos Sartori
2014Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira, et al
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans, et al
2017Sleep Convention Logic Isochronic Fork: an AnalysisRicardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira, et al
Mostrando regs. 9 a 27 de 27   ◄ anterior