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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/13953
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dc.contributor.authorMatheus Gibiluka-
dc.contributor.authorMatheus Trevisan Moreira-
dc.contributor.authorNey Laert Vilar Calazans-
dc.date.accessioned2019-02-11T13:45:31Z-
dc.date.available2019-02-11T13:45:31Z-
dc.date.issued2015-
dc.identifier.urihttp://hdl.handle.net/10923/13953-
dc.language.isoen-
dc.relation.ispartofProceedings of the 18th DSD 2015, 2015, Portugal.-
dc.rightsopenAccess-
dc.subjectAsynchronous Circuits-
dc.subjectasynchronous design-
dc.subjectBundled-Data-
dc.subjectAutomated Synthesis-
dc.titleA Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework-
dc.typeconferenceObject-
dc.date.updated2019-02-11T13:45:30Z-
Appears in Collections:Apresentação em Evento

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