Campo DC | Valor | Idioma |
dc.contributor.author | Matheus Gibiluka | - |
dc.contributor.author | Matheus Trevisan Moreira | - |
dc.contributor.author | Ney Laert Vilar Calazans | - |
dc.date.accessioned | 2019-02-11T13:45:31Z | - |
dc.date.available | 2019-02-11T13:45:31Z | - |
dc.date.issued | 2015 | - |
dc.identifier.uri | http://hdl.handle.net/10923/13953 | - |
dc.language.iso | en | - |
dc.relation.ispartof | Proceedings of the 18th DSD 2015, 2015, Portugal. | - |
dc.rights | openAccess | - |
dc.subject | Asynchronous Circuits | - |
dc.subject | asynchronous design | - |
dc.subject | Bundled-Data | - |
dc.subject | Automated Synthesis | - |
dc.title | A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework | - |
dc.type | conferenceObject | - |
dc.date.updated | 2019-02-11T13:45:30Z | - |
Aparece en las colecciones: | Apresentação em Evento
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