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Results 9951-9960 of 10283 (Search time: 0.008 seconds).
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Issue DateTitleAuthor(s)
2017An Algorithm for Allocating Structured Tasks in Multi-Robot ScenariosTulio L. Basegio; Rafael Heitor Bordini
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2015Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous DesignMatheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
2015TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and OptimizationMatheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel; Ney Laert Vilar Calazans
2013A Flexible Soft IP Core for Standard Implementations of Elliptic Curve Cryptography in HardwareBruno Fin Ferreira; Ney Laert Vilar Calazans
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans