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Resultados 1-9 de 9 (Tiempo de búsqueda: 0.004 Segundos).
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Fecha de PublicaciónTítuloAutor(s)
2015A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA FrameworkMatheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI TechnologiesAjay Singhvi; Matheus Trevisan Moreira; Ramy Nagy Tadros; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck; Leandro Sehnem Heck; Ajay Singhvi; Matheus Trevisan Moreira; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data DesignPeter Anthony Beerel; Ney Laert Vilar Calazans
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang; Matheus Trevisan Moreira; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous DesignMatheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2015TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and OptimizationMatheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel; Ney Laert Vilar Calazans

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