Skip navigation
Home
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Title
Subject
About
About the Institutional Repository
Use Policy
FAQs (Frequently Asked Questions)
Credits
Access Statistics
Sign on to:
My DSpace
Receive email
updates
Edit Profile
Repositório PUCRS
Search
Search:
All Repository
PUBLICAÇÕES CIENTÍFICAS
Apresentação em Evento
for
Current filters:
Title
Author
Subject
Date Issued
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Start a new search
Add filters:
Use filters to refine the search results.
Title
Author
Subject
Date Issued
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Results 1-10 of 73 (Search time: 0.002 seconds).
previous
1
2
3
4
...
8
next
Item hits:
Issue Date
Title
Author(s)
2012
A Generic FPGA Emulation Framework
Fernando Gehm Moraes
;
Matheus Moreira
;
Carlo Lucas
;
Dairan Correa
;
Douglas Cardoso
;
Maurício Magnaguagno
;
Guilherme Castilhos
;
Ney Laert Vilar Calazans
2012
HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping
Guilherme Heck
;
Ricardo Guazzelli
;
Fernando Gehm Moraes
;
Ney Laert Vilar Calazans
;
Rafael Soares
2012
Power Consumption Reduction in MPSoCs through DFS
Thiago Raupp da Rosa
;
Vivian Larréa
;
Ney Laert Vilar Calazans
;
Fernando Gehm Moraes
2012
Impact of C-Elements in Asynchronous Circuits
Matheus Moreira
;
Bruno Oliveira
;
Fernando Gehm Moraes
;
Ney Laert Vilar Calazans
2011
A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCs
Thiago Raupp da Rosa
;
Guilherme Montez Guindani
;
Douglas Maciel Cardoso
;
Ney Laert Vilar Calazans
;
Fernando Gehm Moraes
2011
Adapting a C-Element Design Flow for Low Power
Matheus Moreira
;
Bruno Oliveira
;
Julian Pontes
;
Fernando Gehm Moraes
;
Ney Laert Vilar Calazans
2016
Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications
Felipe Bortolon
;
Matheus Gibiluka
;
Sérgio Johann Filho
;
Sergio Bampi
;
Ney Laert Vilar Calazans
;
Fabiano Passuelo Hessel
;
Matheus Trevisan Moreira
2017
A Comparison of Asynchronous QDI Templates Using Static Logic
Ricardo Aquino Guazzelli
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2017
Go Functional Model for a RISC-V Asynchronous Organization - ARV
Marcos Luiggi Lemos Sartori
;
Ney Laert Vilar Calazans
2015
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework
Matheus Gibiluka
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
Explore
Author
29
Matheus Trevisan Moreira
20
César Augusto Missio Marcon
18
Fernando Gehm Moraes
7
Peter Anthony Beerel
7
Ricardo Aquino Guazzelli
6
Altamiro Amadeu Susin
6
Fabiano Passuelo Hessel
6
MOREIRA, MATHEUS T.
5
Carlos Henrique Menezes Oliveira
5
Matheus Moreira
.
next ►
Subject
26
Asynchronous Circuits
8
asynchronous design
7
Null Convention Logic
6
Standard Cell Library
5
C-element
5
NCL
5
QDI
5
Quasi-Delay Insensitive Circuits
5
Standard Cell
4
Low Power
.
next ►
Issue Date
4
2020 - 2021
53
2010 - 2019
16
2001 - 2009