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Resultados 11-20 de 26 (Tiempo de búsqueda: 0.001 Segundos).

Impacto del ítem:

Fecha de Publicación	Título	Autor(s)
2014	Quasi-Delay-Insensitive Return-to-One Design	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014	Automated Synthesis of Cell Libraries for Asynchronous Circuits	Matheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans
2015	SDDS-NCL Design: Analysis of Supply Voltage Scaling	Ricardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2014	Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2013	ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2013	LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans; Luciano Copello Ost
2012	Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects	PONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2013	H2A: A Hardened Asynchronous Network on Chip	Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014	Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?	Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2013	Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow	Matheus Trevisan Moreira; Ney Laert Vilar Calazans