Percorrendo por Autor Ney Laert Vilar Calazans

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Data de publicaçãoTítuloAutor(es)
2011A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCsThiago Raupp da Rosa; Guilherme Montez Guindani; Douglas Maciel Cardoso, et al
2012A spectrum of MPSoC models for design space exploration and its usePETRY, CARLOS A.; WACHTER, EDUARDO W.; DE CASTILHOS, GUILHERME M., et al
2011Adapting a C-Element Design Flow for Low PowerMatheus Moreira; Bruno Oliveira; Julian Pontes, et al
2012Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event EffectsPONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2012An accurate Single Event Effect digital design flow for reliable system level designPONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2016Analysis and Design of Delay Lines for Dynamic Voltage Scaling ApplicationsRamy Nagy Tadros; Weizhe Hua; Matheus Gibiluka, et al
2015Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck; Leandro Sehnem Heck; Ajay Singhvi, et al
2016ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous DesignCarlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli, et al
2013ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous DesignMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2019Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT VariationsWUERDIG, RODRIGO N.; SARTORI, MARCOS L. L.; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr., et al
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang, et al
2016Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling ApplicationsFelipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho, et al
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2012Electrical characterization of a C-Element with LiChEnMOREIRA, MATHEUS T.; Ney Laert Vilar Calazans
2017Go Functional Model for a RISC-V Asynchronous Organization - ARVMarcos Luiggi Lemos Sartori; Ney Laert Vilar Calazans
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans