1. Repositório PUCRS

Percorrendo por Autor Matheus Trevisan Moreira

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Data de publicaçãoTítuloAutor(es)
2015A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA FrameworkMatheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017A Comparison of Asynchronous QDI Templates Using Static LogicRicardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014A Design Flow for Physical Synthesis of Digital Cells with ASTRANAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI TechnologiesAjay Singhvi; Matheus Trevisan Moreira; Ramy Nagy Tadros, et al
2014A New CMOS Topology for Low-Voltage Null Convention Logic Gates DesignMatheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli, et al
2018An LSSD Compliant Scan Cell for Flip-FlopsJURACY, LEONARDO; Matheus Trevisan Moreira; KUENTZER, FELIPE A., et al
2016Analysis and Design of Delay Lines for Dynamic Voltage Scaling ApplicationsRamy Nagy Tadros; Weizhe Hua; Matheus Gibiluka, et al
2015Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck; Leandro Sehnem Heck; Ajay Singhvi, et al
2016ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous DesignCarlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli, et al
2013ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous DesignMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr., et al
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang, et al
2016Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling ApplicationsFelipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho, et al
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, et al
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
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