Please use this identifier to cite or link to this item: http://hdl.handle.net/10923/13492
Type: conferenceObject
Title: HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping
Author(s): Guilherme Heck
Ricardo Guazzelli
Fernando Gehm Moraes
Ney Laert Vilar Calazans
Rafael Soares
In: VIII Southern Programmable Logic Conference, 2012, Brasil.
Issue Date: 2012
Keywords: NOC - Redes Intra-chip
FPGA
Prototipação
URI: http://hdl.handle.net/10923/13492
DOI: DOI:10.1109/SPL.2012.6211781
ISBN: 9781467301855
Appears in Collections:Apresentação em Evento

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