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Resultados 12051-12060 de 24668 (Tiempo de búsqueda: 0.006 Segundos).
Impacto del ítem:
Fecha de PublicaciónTítuloAutor(s)
2015Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck; Leandro Sehnem Heck; Ajay Singhvi; Matheus Trevisan Moreira; Ney Laert Vilar Calazans; Peter Anthony Beerel
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data DesignPeter Anthony Beerel; Ney Laert Vilar Calazans
2016ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous DesignCarlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
2016Early Approaches to Anaphora Resolution: Theoretically Inspired and Heuristic-BasedMassimo Poesio; Stuckardt, Roland; Versley, Yannick; Renata Vieira
2014A New CMOS Topology for Low-Voltage Null Convention Logic Gates DesignMatheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang; Matheus Trevisan Moreira; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2017An Algorithm for Allocating Structured Tasks in Multi-Robot ScenariosTulio L. Basegio; Rafael Heitor Bordini
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans

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