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Resultados 12061-12080 de 24685 (Tiempo de búsqueda: 0.006 Segundos).
Impacto del ítem:
Fecha de PublicaciónTítuloAutor(s)
2015Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous DesignMatheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
2015TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and OptimizationMatheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel; Ney Laert Vilar Calazans
2013A Flexible Soft IP Core for Standard Implementations of Elliptic Curve Cryptography in HardwareBruno Fin Ferreira; Ney Laert Vilar Calazans
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2013ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous DesignMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2014A Design Flow for Physical Synthesis of Digital Cells with ASTRANAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2013Parity Check for m-of-n Delay Insensitive CodesJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins; André Inácio Reis; Renato Perez Ribas; Ney Laert Vilar Calazans
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans; Luciano Copello Ost
2012Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event EffectsPONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2012An accurate Single Event Effect digital design flow for reliable system level designPONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2013Voltage Scaling on C-Elements: A Speed, Power and Energy Efficiency AnalysisMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2017Portuguese Personal Story Analysis and Detection in BlogsHenrique Dias; Vinicius Woloszyn; Renata Vieira
Resultados 12061-12080 de 24685 (Tiempo de búsqueda: 0.006 Segundos).

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