1. Repositório PUCRS

Visualizando por Autor Ney Laert Vilar Calazans

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Fecha de PublicaciónTítuloAutor(s)
2016Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling ApplicationsFelipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho, etc.
2005Design and Prototyping of an SDH-E1 Mapper Soft-coreCésar Augusto Missio Marcon; José Santanna Palma; Ney Laert Vilar Calazans, etc.
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, etc.
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2005Design, Validation and Prototyping of the EMS SDH STM-1 Mapper Soft-coreNey Laert Vilar Calazans; Fernando Gehm Moraes; César Augusto Missio Marcon, etc.
2001Effective Industry-Academia Cooperation in Telecom: a Method, a Case Study and Some Initial ResultsNey Laert Vilar Calazans; Fernando Gehm Moraes; César Augusto Missio Marcon, etc.
2012Electrical characterization of a C-Element with LiChEnMOREIRA, MATHEUS T.; Ney Laert Vilar Calazans
2005Energy and Latency Evaluation of NoC TopologiesKREUTZ, M.; César Augusto Missio Marcon; Carro, L., etc.
2007Evaluation of Algorithms for Low Energy Mapping onto NoCsCésar Augusto Missio Marcon; Edson I. Moreno; Ney Laert Vilar Calazans, etc.
2009Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCsCARVALHO, EWERSON; César Augusto Missio Marcon; Ney Laert Vilar Calazans, etc.
2005Exploring NoC Mapping Strategies: An Energy and Timing Aware TechniqueCésar Augusto Missio Marcon; Ney Laert Vilar Calazans; MORAES, F., etc.
2017Go Functional Model for a RISC-V Asynchronous Organization - ARVMarcos Luiggi Lemos Sartori; Ney Laert Vilar Calazans
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, etc.
2012HardNoC: A Platform to Validate Networks on Chip through FPGA PrototypingGuilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes, etc.
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes, etc.
2013Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancyYan Ghidini de Souza; Matheus Moreira; Lucas Brahm, etc.
2020Leveraging QDI Robustness to Simplify the Design of IoT CircuitsSARTORI, MARCOS L. L.; WUERDIG, RODRIGO N.; MOREIRA, MATHEUS T., etc.
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, etc.
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