Browsing by Author Ney Laert Vilar Calazans

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Showing rec. 30 to 47 of 47   ◄ previous   
Issue DateTitleAuthor(s)
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, et al
2012HardNoC: A Platform to Validate Networks on Chip through FPGA PrototypingGuilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes, et al
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes, et al
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Parity Check for m-of-n Delay Insensitive CodesJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2012Power Consumption Reduction in MPSoCs through DFSThiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans, et al
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2012Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuitsMOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
2012Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codesMOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
2014Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira, et al
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans, et al
2014Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins, et al
2017Sleep Convention Logic Isochronic Fork: an AnalysisRicardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira, et al
2015TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and OptimizationMatheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel, et al
2015Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous DesignMatheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2013Voltage Scaling on C-Elements: A Speed, Power and Energy Efficiency AnalysisMatheus Trevisan Moreira; Ney Laert Vilar Calazans