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Repositório PUCRS
Browsing by Subject Asynchronous Circuits
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Showing rec. 1 to 20 of 27
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Issue Date
Title
Author(s)
2011
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design
MOREIRA, MATHEUS
;
OLIVEIRA, BRUNO
;
PONTES, JULIAN
, et al
2015
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework
Matheus Gibiluka
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2017
A Comparison of Asynchronous QDI Templates Using Static Logic
Ricardo Aquino Guazzelli
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2020
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
SARTORI, MARCOS L. L.
;
MOREIRA, MATHEUS T.
;
Ney Laert Vilar Calazans
2015
A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data Design
Peter Anthony Beerel
;
Ney Laert Vilar Calazans
2012
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects
PONTES, JULIAN
;
Ney Laert Vilar Calazans
;
VIVET, PASCAL
2015
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
Guilherme Heck
;
Leandro Sehnem Heck
;
Ajay Singhvi
, et al
2016
ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous Design
Carlos Henrique Menezes Oliveira
;
Matheus Trevisan Moreira
;
Ricardo Aquino Guazzelli
, et al
2013
ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ney Laert Vilar Calazans
2019
Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations
WUERDIG, RODRIGO N.
;
SARTORI, MARCOS L. L.
;
Ney Laert Vilar Calazans
2019
Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations
WUERDIG, RODRIGO N.
;
SARTORI, MARCOS L. L.
;
Ney Laert Vilar Calazans
2014
Automated Synthesis of Cell Libraries for Asynchronous Circuits
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Adriel Ziesemer Jr.
, et al
2014
Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells
Adriel Ziesemer Jr.
;
Ricardo Augusto da Luz Reis
;
Matheus Trevisan Moreira
, et al
2015
Blade - A Timing Violation Resilient Asynchronous Template
Dylan Hand
;
Matheus Trevisan Moreira
;
Hsin-Ho Huang
, et al
2013
Design of NCL Gates with the ASCEnD Flow
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ricardo Cademartori Porto
, et al
2013
Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2013
H2A: A Hardened Asynchronous Network on Chip
Julian José Hilgemberg Pontes
;
Ney Laert Vilar Calazans
;
Pascal Vivet
2017
Hardening C-elements Against Metastability
Leandro Sehnem Heck
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2013
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ney Laert Vilar Calazans
, et al
2015
Performance Optimization and Analysis of Blade Designs Under Delay Variability
Dylan Hand
;
Hsin-Ho Huang
;
Benmao Cheng
, et al