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Issue Date	Title	Author(s)
2016	ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous Design	Carlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
2014	A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design	Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
2015	Performance Optimization and Analysis of Blade Designs Under Delay Variability	Dylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang; Matheus Trevisan Moreira; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2013	Design of NCL Gates with the ASCEnD Flow	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2014	Quasi-Delay-Insensitive Return-to-One Design	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015	Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous Design	Matheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2014	Automated Synthesis of Cell Libraries for Asynchronous Circuits	Matheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans
2015	SDDS-NCL Design: Analysis of Supply Voltage Scaling	Ricardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2014	Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis	Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck; Ney Laert Vilar Calazans
2015	TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization	Matheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel; Ney Laert Vilar Calazans