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Results 1-10 of 23 (Search time: 0.001 seconds).
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Issue DateTitleAuthor(s)
2017A Comparison of Asynchronous QDI Templates Using Static LogicRicardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA FrameworkMatheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2017Sleep Convention Logic Isochronic Fork: an AnalysisRicardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck; Leandro Sehnem Heck; Ajay Singhvi; Matheus Trevisan Moreira; Ney Laert Vilar Calazans; Peter Anthony Beerel
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data DesignPeter Anthony Beerel; Ney Laert Vilar Calazans
2016ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous DesignCarlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Ney Laert Vilar Calazans
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang; Matheus Trevisan Moreira; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans