| DC Field | Value | Language |
|---|
| dc.contributor.author | Adriel Ziesemer Jr. | - |
| dc.contributor.author | Ricardo Augusto da Luz Reis | - |
| dc.contributor.author | Matheus Trevisan Moreira | - |
| dc.contributor.author | Michel Evandro Arendt | - |
| dc.contributor.author | Ney Laert Vilar Calazans | - |
| dc.date.accessioned | 2019-02-12T12:04:54Z | - |
| dc.date.available | 2019-02-12T12:04:54Z | - |
| dc.date.issued | 2014 | - |
| dc.identifier.uri | http://hdl.handle.net/10923/13968 | - |
| dc.language.iso | en | - |
| dc.relation.ispartof | Proceedings of the 24th GLSVLSI 2014, 2014, Estados Unidos. | - |
| dc.rights | openAccess | - |
| dc.subject | CAD | - |
| dc.subject | Standard Cell | - |
| dc.subject | EDA | - |
| dc.subject | Cell Synthesis | - |
| dc.subject | Layout Generation | - |
| dc.title | A Design Flow for Physical Synthesis of Digital Cells with ASTRAN | - |
| dc.type | conferenceObject | - |
| dc.date.updated | 2019-02-12T12:04:53Z | - |
| Appears in Collections: | Apresentação em Evento
|
