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Results 51-60 of 78 (Search time: 0.001 seconds).
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Issue DateTitleAuthor(s)
2020A Frontend using Traditional EDA Tools for the Pulsar QDI Design FlowSARTORI, MARCOS L. L.; MOREIRA, MATHEUS T.; Ney Laert Vilar Calazans
2021Quasi Delay Insensitive FIFOs: Design Choices Exploration and ComparisonRODOLFO, TACIANO A.; SARTORI, MARCOS L. L.; MOREIRA, MATHEUS T.; Ney Laert Vilar Calazans
2019Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT VariationsWUERDIG, RODRIGO N.; SARTORI, MARCOS L. L.; Ney Laert Vilar Calazans
2021Robust and Energy-Efficient Hardware: The Case for Asynchronous DesignNey Laert Vilar Calazans; Taciano Ares Rodolfo; Marcos Luiggi Lemos Sartori
2020Leveraging QDI Robustness to Simplify the Design of IoT CircuitsSARTORI, MARCOS L. L.; WUERDIG, RODRIGO N.; MOREIRA, MATHEUS T.; BAMPI, SERGIO; Ney Laert Vilar Calazans
2011CAFES: A framework for intrachip application modeling and communication architecture designCésar Augusto Missio Marcon; Ney Laert Vilar Calazans; Fabiano Passuelo Hessel; Fernando Gehm Moraes; Altamiro Amadeu Susin; Edson I. Moreno
2005Design and Prototyping of an SDH-E1 Mapper Soft-coreCésar Augusto Missio Marcon; José Santanna Palma; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2014MoNoC: A monitored network on chip with path adaptation mechanismMORENO, EDSON; Thais Christina Webber Dos Santos; César Augusto Missio Marcon; MORAES, FERNANDO; Ney Laert Vilar Calazans
2011Arbitration and routing impact on NoC designEdson I. Moreno; César Augusto Missio Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes
2014A monitored NoC with runtime path adaptationEdson I. Moreno; Thais Christina Webber Dos Santos; César Augusto Missio Marcon; Fernando Gehm Moraes; Ney Laert Vilar Calazans