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Browsing by Author Matheus Trevisan Moreira

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Issue Date	Title	Author(s)
2015	A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework	Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017	A Comparison of Asynchronous QDI Templates Using Static Logic	Ricardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014	A Design Flow for Physical Synthesis of Digital Cells with ASTRAN	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015	A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies	Ajay Singhvi; Matheus Trevisan Moreira; Ramy Nagy Tadros, et al
2014	A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design	Matheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli, et al
2018	An LSSD Compliant Scan Cell for Flip-Flops	JURACY, LEONARDO; Matheus Trevisan Moreira; KUENTZER, FELIPE A., et al
2016	Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications	Ramy Nagy Tadros; Weizhe Hua; Matheus Gibiluka, et al
2015	Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits	Guilherme Heck; Leandro Sehnem Heck; Ajay Singhvi, et al
2016	ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous Design	Carlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli, et al
2013	ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2014	Automated Synthesis of Cell Libraries for Asynchronous Circuits	Matheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr., et al
2014	Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells	Adriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015	Blade - A Timing Violation Resilient Asynchronous Template	Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang, et al
2016	Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications	Felipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho, et al
2013	Design of NCL Gates with the ASCEnD Flow	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013	Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017	Hardening C-elements Against Metastability	Leandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014	Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis	Matheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, et al
2013	LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2013	NCL+: Return-to-One Null Convention Logic	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al

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