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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/12271
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dc.contributor.authorJuliano Benfica-
dc.contributor.authorGREEN, BRUNO-
dc.contributor.authorPORCHER, BRUNO C.-
dc.contributor.authorLetícia Maria Bolzani Pöhls-
dc.contributor.authorFabian Vargas-
dc.contributor.authorMEDINA, NILBERTO H.-
dc.contributor.authorADDED, NEMITALA-
dc.contributor.authorDE AGUIAR, VITOR A. P.-
dc.contributor.authorMACCHIONE, EDUARDO L. A.-
dc.contributor.authorAGUIRRE, FERNANDO-
dc.contributor.authorDA SILVEIRA, MARCILEI A. G.-
dc.date.accessioned2018-07-30T14:41:23Z-
dc.date.available2018-07-30T14:41:23Z-
dc.date.issued2016-
dc.identifier.isbn9781467394949-
dc.identifier.urihttp://hdl.handle.net/10923/12271-
dc.language.isopt_BR-
dc.relation.ispartof2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), 2016, Brasil.-
dc.rightsopenAccess-
dc.titleAnalysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID-
dc.typeconferenceObject-
dc.date.updated2018-07-30T14:41:22Z-
dc.identifier.doiDOI:10.1109/APEMC.2016.7522900-
Appears in Collections:Apresentação em Evento

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