| Campo DC | Valor | Idioma |
|---|
| dc.contributor.author | Marcos Luiggi Lemos Sartori | - |
| dc.contributor.author | Rodrigo Nogueira Wuerdig | - |
| dc.contributor.author | Matheus Trevisan Moreira | - |
| dc.contributor.author | Ney Laert Vilar Calazans | - |
| dc.date.accessioned | 2021-11-30T11:17:18Z | - |
| dc.date.available | 2021-11-30T11:17:18Z | - |
| dc.date.issued | 2019 | - |
| dc.identifier.uri | https://hdl.handle.net/10923/19994 | - |
| dc.language.iso | en | - |
| dc.relation.ispartof | ASYNC´19, 2019, Japão. | - |
| dc.rights | openAccess | - |
| dc.subject | Síntese Automatizada | - |
| dc.subject | Circuitos Assíncronos | - |
| dc.subject | EDA | - |
| dc.title | Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools | - |
| dc.type | conferenceObject | - |
| dc.date.updated | 2021-11-30T11:17:17Z | - |
| Aparece en las colecciones: | Apresentação em Evento
|
