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Repositório PUCRS
Browsing by Author Matheus Trevisan Moreira
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Showing rec. 10 to 29 of 31
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Issue Date
Title
Author(s)
2013
ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous Design
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ney Laert Vilar Calazans
2014
Automated Synthesis of Cell Libraries for Asynchronous Circuits
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Adriel Ziesemer Jr.
, et al
2014
Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells
Adriel Ziesemer Jr.
;
Ricardo Augusto da Luz Reis
;
Matheus Trevisan Moreira
, et al
2015
Blade - A Timing Violation Resilient Asynchronous Template
Dylan Hand
;
Matheus Trevisan Moreira
;
Hsin-Ho Huang
, et al
2016
Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling Applications
Felipe Bortolon
;
Matheus Gibiluka
;
Sérgio Johann Filho
, et al
2013
Design of NCL Gates with the ASCEnD Flow
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ricardo Cademartori Porto
, et al
2013
Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2017
Hardening C-elements Against Metastability
Leandro Sehnem Heck
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2014
Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis
Matheus Trevisan Moreira
;
Ricardo Aquino Guazzelli
;
Guilherme Heck
, et al
2013
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ney Laert Vilar Calazans
, et al
2013
NCL+: Return-to-One Null Convention Logic
Matheus Trevisan Moreira
;
Carlos Henrique Menezes Oliveira
;
Ricardo Cademartori Porto
, et al
2015
Performance Optimization and Analysis of Blade Designs Under Delay Variability
Dylan Hand
;
Hsin-Ho Huang
;
Benmao Cheng
, et al
2019
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
Marcos Luiggi Lemos Sartori
;
Rodrigo Nogueira Wuerdig
;
Matheus Trevisan Moreira
, et al
2014
Quasi-Delay-Insensitive Return-to-One Design
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2014
Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?
Ricardo Aquino Guazzelli
;
Guilherme Heck
;
Matheus Trevisan Moreira
, et al
2015
SDDS-NCL Design: Analysis of Supply Voltage Scaling
Ricardo Aquino Guazzelli
;
Fernando Gehm Moraes
;
Ney Laert Vilar Calazans
, et al
2014
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
Matheus Trevisan Moreira
;
Augusto Neutzling Silva
;
Mayler Gama Alvarenga Martins
, et al
2017
Sleep Convention Logic Isochronic Fork: an Analysis
Ricardo Aquino Guazzelli
;
Walter Lau Neto
;
Matheus Trevisan Moreira
, et al
2015
TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization
Matheus Trevisan Moreira
;
Dylan Hand
;
Peter Anthony Beerel
, et al
2018
Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template
KUENTZER, FELIPE A.
;
JURACY, LEONARDO
;
Matheus Trevisan Moreira
, et al