Percorrendo por Autor Matheus Trevisan Moreira

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Data de publicaçãoTítuloAutor(es)
2013ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous DesignMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr., et al
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang, et al
2016Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling ApplicationsFelipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho, et al
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, et al
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira, et al
2015SDDS-NCL Design: Analysis of Supply Voltage ScalingRicardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans, et al
2014Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins, et al
2017Sleep Convention Logic Isochronic Fork: an AnalysisRicardo Aquino Guazzelli; Walter Lau Neto; Matheus Trevisan Moreira, et al
2015TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and OptimizationMatheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel, et al
2018Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient TemplateKUENTZER, FELIPE A.; JURACY, LEONARDO; Matheus Trevisan Moreira, et al
2015Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous DesignMatheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans