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Mostrando regs. 1 a 20 de 78
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Data de publicação
Título
Autor(es)
2011
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design
MOREIRA, MATHEUS
;
OLIVEIRA, BRUNO
;
PONTES, JULIAN
, et al
2015
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework
Matheus Gibiluka
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2017
A Comparison of Asynchronous QDI Templates Using Static Logic
Ricardo Aquino Guazzelli
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2014
A Design Flow for Physical Synthesis of Digital Cells with ASTRAN
Adriel Ziesemer Jr.
;
Ricardo Augusto da Luz Reis
;
Matheus Trevisan Moreira
, et al
2021
A differential IR-UWB transmitter using PAM modulation with adaptive PSD
MOREIRA, LUIZ CARLOS
;
VICTOR, MARCUS HENRIQUE
;
SAOTOME, OSAMU
, et al
2015
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies
Ajay Singhvi
;
Matheus Trevisan Moreira
;
Ramy Nagy Tadros
, et al
2013
A Flexible Soft IP Core for Standard Implementations of Elliptic Curve Cryptography in Hardware
Bruno Fin Ferreira
;
Ney Laert Vilar Calazans
2020
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
SARTORI, MARCOS L. L.
;
MOREIRA, MATHEUS T.
;
Ney Laert Vilar Calazans
2012
A Generic FPGA Emulation Framework
Fernando Gehm Moraes
;
Matheus Moreira
;
Carlo Lucas
, et al
2014
A monitored NoC with runtime path adaptation
Edson I. Moreno
;
Thais Christina Webber Dos Santos
;
César Augusto Missio Marcon
, et al
2014
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Ricardo Aquino Guazzelli
, et al
2015
A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data Design
Peter Anthony Beerel
;
Ney Laert Vilar Calazans
2011
A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCs
Thiago Raupp da Rosa
;
Guilherme Montez Guindani
;
Douglas Maciel Cardoso
, et al
2012
A spectrum of MPSoC models for design space exploration and its use
PETRY, CARLOS A.
;
WACHTER, EDUARDO W.
;
DE CASTILHOS, GUILHERME M.
, et al
2011
Adapting a C-Element Design Flow for Low Power
Matheus Moreira
;
Bruno Oliveira
;
Julian Pontes
, et al
2012
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects
PONTES, JULIAN
;
Ney Laert Vilar Calazans
;
VIVET, PASCAL
2012
An accurate Single Event Effect digital design flow for reliable system level design
PONTES, J.
;
Ney Laert Vilar Calazans
;
Pascal Vivet
2016
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications
Ramy Nagy Tadros
;
Weizhe Hua
;
Matheus Gibiluka
, et al
2015
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
Guilherme Heck
;
Leandro Sehnem Heck
;
Ajay Singhvi
, et al
2004
Applying Memory Test to Embedded Systems
César Augusto Missio Marcon
;
Alexandre Amory
;
Marcelo Lubaszewski
, et al