Browsing by Author Ney Laert Vilar Calazans

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Issue DateTitleAuthor(s)
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, et al
2015Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang, et al
2016Design and Analysis of the HF-RISC Processor Targeting Voltage Scaling ApplicationsFelipe Bortolon; Matheus Gibiluka; Sérgio Johann Filho, et al
2013Design of NCL Gates with the ASCEnD FlowMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2012Electrical characterization of a C-Element with LiChEnMOREIRA, MATHEUS T.; Ney Laert Vilar Calazans
2017Go Functional Model for a RISC-V Asynchronous Organization - ARVMarcos Luiggi Lemos Sartori; Ney Laert Vilar Calazans
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, et al
2012HardNoC: A Platform to Validate Networks on Chip through FPGA PrototypingGuilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes, et al
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes, et al
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Parity Check for m-of-n Delay Insensitive CodesJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2012Power Consumption Reduction in MPSoCs through DFSThiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans, et al
2014Quasi-Delay-Insensitive Return-to-One DesignMatheus Trevisan Moreira; Ney Laert Vilar Calazans
2012Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuitsMOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans
2012Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codesMOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans