Visualizando por Autor Ney Laert Vilar Calazans

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Fecha de PublicaciónTítuloAutor(s)
2011A 65nm standard cell set and flow dedicated to automated asynchronous circuits designMOREIRA, MATHEUS; OLIVEIRA, BRUNO; PONTES, JULIAN, etc.
2015A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA FrameworkMatheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017A Comparison of Asynchronous QDI Templates Using Static LogicRicardo Aquino Guazzelli; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014A Design Flow for Physical Synthesis of Digital Cells with ASTRANAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, etc.
2015A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI TechnologiesAjay Singhvi; Matheus Trevisan Moreira; Ramy Nagy Tadros, etc.
2013A Flexible Soft IP Core for Standard Implementations of Elliptic Curve Cryptography in HardwareBruno Fin Ferreira; Ney Laert Vilar Calazans
2012A Generic FPGA Emulation FrameworkFernando Gehm Moraes; Matheus Moreira; Carlo Lucas, etc.
2014A New CMOS Topology for Low-Voltage Null Convention Logic Gates DesignMatheus Trevisan Moreira; Michel Evandro Arendt; Ricardo Aquino Guazzelli, etc.
2015A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data DesignPeter Anthony Beerel; Ney Laert Vilar Calazans
2011A Self-adaptable Distributed DFS Scheme for NoC-based MPSoCsThiago Raupp da Rosa; Guilherme Montez Guindani; Douglas Maciel Cardoso, etc.
2012A spectrum of MPSoC models for design space exploration and its usePETRY, CARLOS A.; WACHTER, EDUARDO W.; DE CASTILHOS, GUILHERME M., etc.
2011Adapting a C-Element Design Flow for Low PowerMatheus Moreira; Bruno Oliveira; Julian Pontes, etc.
2012Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event EffectsPONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2012An accurate Single Event Effect digital design flow for reliable system level designPONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2016Analysis and Design of Delay Lines for Dynamic Voltage Scaling ApplicationsRamy Nagy Tadros; Weizhe Hua; Matheus Gibiluka, etc.
2015Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data CircuitsGuilherme Heck; Leandro Sehnem Heck; Ajay Singhvi, etc.
2016ASCEnD-FreePDK45: An Open Source StandardCell Library for Asynchronous DesignCarlos Henrique Menezes Oliveira; Matheus Trevisan Moreira; Ricardo Aquino Guazzelli, etc.
2013ASCEnD: A Standard Cell Library for Semi-Custom Asynchronous DesignMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans
2014Automated Synthesis of Cell Libraries for Asynchronous CircuitsMatheus Trevisan Moreira; Michel Evandro Arendt; Adriel Ziesemer Jr., etc.
2014Automatic Layout Synthesis with ASTRAN Applied to Asynchronous CellsAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira, etc.