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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/13956
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DC FieldValueLanguage
dc.contributor.authorRicardo Aquino Guazzelli-
dc.contributor.authorWalter Lau Neto-
dc.contributor.authorMatheus Trevisan Moreira-
dc.contributor.authorNey Laert Vilar Calazans-
dc.date.accessioned2019-02-11T13:45:46Z-
dc.date.available2019-02-11T13:45:46Z-
dc.date.issued2017-
dc.identifier.urihttp://hdl.handle.net/10923/13956-
dc.language.isoen-
dc.relation.ispartofSBCCI`17, 2017, Brasil.-
dc.rightsopenAccess-
dc.subjectAsynchronous Circuits-
dc.subjectasynchronous design-
dc.subjectQuasi-Delay Insensitive Circuits-
dc.subjectQDI-
dc.subjectNCL-
dc.subjectSCL-
dc.titleSleep Convention Logic Isochronic Fork: an Analysis-
dc.typeconferenceObject-
dc.date.updated2019-02-11T13:45:45Z-
Appears in Collections:Apresentação em Evento

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