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DOCUMENTOS INSTITUCIONAIS
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TRABALHOS DE CONCLUSÃO DE CURSO DE GRADUAÇÃO
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Issue Date
Title
Author(s)
2012
HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping
Guilherme Heck
;
Ricardo Guazzelli
;
Fernando Gehm Moraes
;
Ney Laert Vilar Calazans
;
Rafael Soares
2015
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
Guilherme Heck
;
Leandro Sehnem Heck
;
Ajay Singhvi
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
;
Peter Anthony Beerel
2014
Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis
Matheus Trevisan Moreira
;
Ricardo Aquino Guazzelli
;
Guilherme Heck
;
Ney Laert Vilar Calazans
2014
Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?
Ricardo Aquino Guazzelli
;
Guilherme Heck
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
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Author
3
Matheus Trevisan Moreira
2
Ricardo Aquino Guazzelli
1
Ajay Singhvi
1
Fernando Gehm Moraes
1
Leandro Sehnem Heck
1
Peter Anthony Beerel
1
Rafael Soares
1
Ricardo Guazzelli
Subject
2
Asynchronous Circuits
1
Delay Element
1
Delay Insensitive Maxterm Synthesis
1
FPGA
1
Hardening
1
NOC - Redes Intra-chip
1
Null Convention Logic
1
Prototipação
1
Quasi-Delay Insensitive Circuits
1
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