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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/15212
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dc.contributor.authorKUENTZER, FELIPE A.-
dc.contributor.authorJURACY, LEONARDO-
dc.contributor.authorMatheus Trevisan Moreira-
dc.contributor.authorAlexandre de Morais Amory-
dc.date.accessioned2019-07-29T19:13:11Z-
dc.date.available2019-07-29T19:13:11Z-
dc.date.issued2018-
dc.identifier.urihttp://hdl.handle.net/10923/15212-
dc.language.isopt_BR-
dc.relation.ispartofSymposium on Integrated Circuits and Systems Design (SBCCI), 2018, Brasil.-
dc.rightsopenAccess-
dc.subjectProjeto Visando o Teste-
dc.subjectprojeto assíncrono-
dc.titleTestable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template-
dc.typeconferenceObject-
dc.date.updated2019-07-29T19:13:10Z-
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