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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/18523
Type: Article
Title: Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy
Author(s): VILLA, PAULO R. C.
TRAVESSINI, RODRIGO
GOERL, ROGER C.
Fabian Luis Vargas
BEZERRA, EDUARDO A.
In: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Issue Date: 2019
Volume: 1
First page: 1
Keywords: Fault-tolerance
Checkpoint recovery
Soft-core processors
FPGAs
Single-event upsets
URI: https://hdl.handle.net/10923/18523
DOI: DOI:10.1007/s10836-019-05778-z
ISSN: 0923-8174
Appears in Collections:Artigo de Periódico

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